1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device such as a one-transistor-one-capacitor type dynamic random access memory.
2. Description of the Related Art
A dynamic random access memory (DRAM) constituted by one-transistor-one-capacitor type memory cells has recently been improved rapidly in degree of integration and memory capacity, in virtue of the progress in semi-conductor technology, especially fine processing technology. There is a substrate plate trench (SPT) cell as a cell having a flat surface and a high capacitance of a capacitor.
The structure of the SPT cell will now be described, with reference to FIG. 8. A P-type epitaxial layer 52 is formed on P.sup.+ -type silicon substrate 51 serving as a cell plate of the memory cell, and an N well region 53 is selectively formed in the P-type epitaxial layer 52. A trench 54 is formed so as to penetrate both the N well region 53 and the epitaxial layer 52 and reach the inside of the P.sup.+ -type silicon substrate 51. The trench 54 is filled with P.sup.+ -type polysilicon 56 serving as a storage node of the memory cell, with a gate insulating film 55 formed on the inner surface of the trench 54. A silicon oxide film 57 is selectively formed on the surface of the substrate. A P.sup.+ -type diffusion layer 58 serving as a diffusion region of a PMOS transistor is formed in the N well region 53, and a P-type diffusion layer 59 serving as a plate electrode removing region is formed in the P-type epitaxial layer 52. The P.sup.+ -type polysilicon 56 and P.sup.+ -type diffusion layer 58 are electrically connected to each other by a conductive strap 60. A transfer gate 61 serving as a gate of the PMOS transistor is formed above the N well region 53 with an insulating film 62 interposed between them. Finally, a wiring layer 63 is selectively formed.
Since the SPT cell as shown in FIG. 8 is able to obtain a high capacitance of the capacitor in virtue of the trench 54 and the P.sup.+ -type silicon substrate 51 serves as a cell plate, the SPT cell can be formed to have a flat surface. It is however evident that only the P.sup.+ -type silicon substrate 51 contributes to the high capacitance of the capacitor and neither the P-type epitaxial layer 52 nor the N well region 53 contributes to the high capacitance of the capacitor.
The capacitance of the capacitor can be increased further by thinning the N well region 53 and the P-type epitaxial layer 52. However, a leak occurs owing to a parasitic FET in the longitudinal direction of the P.sup.+ -type diffusion layer 58, N well region 53, and P-type epitaxial layer 52. If the N well region 53 is thinned while keeping a constant concentration, the sheet resistance of the N well region 53 is heightened, the potential of the N well region 53 locally becomes unstable, and the operation of the transfer gate 61 becomes unstable. As described above, the N well region 53 and P-type epitaxial layer 52 need to have a predetermined thickness, and they cannot be thinned too much.
Further, the plate electrode removing region has to be contacted, excepting where the N well region 53 is formed. Since, however, the N well region 53 is deep, the semiconductor memory device requires a region extended sufficiently in the lateral direction, which prevents the device from improving in high degree of integration.